8 HOURS DELIVERY: PLAGIARISM FREE AND QUALITY WORK GUARANTEED.

To design a D and T flip-flops(FF) using JK FF. To understand the usage of FFs a

To design a D and T flip-flops(FF) using JK FF.
To understand the usage of FFs as clock dividers and to witness an influence of excessive capacitance on
signals. PROCEDURE 1) Given JK FF verify FF switching behavior by obtaining a truth table specific to this chip.
You are expected to get FF with different input values (e.g. J =0, K=1), then leverage a logic
analyzer to measure the two outputs waveform. Then compare the output value with the truth
table in the slides.Note: please go through attached i provide remaining question and lab formatplease do simulation in EasyEDA and provide screenshot.
Requirements: provide answers   |   .doc file